Gary Plunkett: Detailed CV

VHDL

Engineering Design Project

As part of my Engineering Design course I designed a Phone Appliance Control System. This system was implemented using VHDL and an ASIC board. The device was used to answer a phone and take user input to control household appliances. The ASIC board was interfaced with a phone line and relays which were to control appliances. The VHDL code determined when to answer the phone, interpreted keypad input and sent signals to turn an appliance on or off. The key entry format allowed the user to enter a time for the appliance to turn on or off at.

Links:

Phone Appliance Control System - Technical Paper (with VHDL code)

I have also used the following programming environment for VHDL:

Altera Max+ II

CPU Architecture

As part of labratory work for a course in computer architecture I worked as part of a team to implemented a simple 5 stage pipelined RISC CPU using Altera Max+ II in VHDL. Timing analysis was done to determine highest clock rates for the particular ASIC board we were using. Each stage was designed as a separate block and tested individually.

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